1. Field of the Invention
The present invention relates to the field of computer memories, and more particularly, to an apparatus and process for advantageously programming into a memory controller timing data used to generate timing signals for the memory modules coupled to the memory controller.
2. Art Background
Computer systems commonly utilize banks of dynamic random access memory (DRAM) for storing data and computer programs for a variety of tasks. For example, in a bit map computer display system, each pixel disposed on a cathode ray tube (CRT) display is assigned a single bit digital value to represent the pixel in memory, or a multiple bit digital value to represent color. Computers have traditionally addressed their memories in 8 bit, 16 bit, 32 bit, 64 bit or larger increments. Typically one memory cycle has the capability of transferring a predetermined number of bits. Over the years since the advent of digital computers, a variety of memory configurations and architectures have been developed to maximize the performance of data processing systems.
A number of computing systems, such as the engineering workstations manufactured by the assignee of the present application, Sun Microsystems, Inc., have provided dynamic RAM memory through the use of DRAM modules, which plug into the main printed circuit board ("mother board") of the workstation. These DRAM modules provide a known amount of memory per module, with predetermined cycle times and operating modes. For example, a DRAM module offered by the Toshiba Corporation provides 72 megabits, 36 megabits, and other combinations of RAM storage capacity, on printed circuit boards for insertion into memory expansion slots on computer mother boards.
Application Ser. No. 07/554,283, filed Jul. 17, 1990, of which this application is a continuation-in-part, disclosed an improved single in-line memory module containing a plurality of DRAMs for use in a digital computing system. The data processing system disclosed in that application utilized multiple memory modules, known as SIMMs. Each of these SIMMs contained DRAMs, and each of these DRAMs provided a known amount of memory with predetermined cycle times and operating modes.
Typically, within a system using multiple memory modules, the timing of the memory operations is fixed or hard-wired. This fixed timing, however, can present problems when replacement or substitution of DRAMs is desired. As a general matter, various DRAMs with various timing requirements are presently available on the market. Frequently, the timing requirements of a first vendor's DRAMs are different from the timing requirements of a second vendor's DRAMs. A data processing system which has fixed timing, therefore, does not necessarily allow an individual to replace the first vendor's DRAMs with the second vendor's DRAMs. In particular, within a SIMM system, fixed timing does not facilitate the replacement of a first group of SIMMs containing a first vendor's DRAMs with a second group of SIMMs containing a second vendor's DRAMs.
Perhaps most significantly, fixed timing does not allow a data processing system to take advantage of advances in DRAM timing. Each new generation of DRAMs tends to achieve faster cycle times than the previous generation of DRAMs. Ideally then, a data processing system should have programmable timing, able to adapt to each new, faster generation of DRAMs.
As will be described, the apparatus of the present invention provides for programmable memory timing in a data processing system. Once properly programmed, the programmable memory timing provides optimal timing signals for all memory operations. The present invention, therefore, allows the data processing system to readily adapt to, and take advantage of, DRAMs with different timing requirements.